1. Field of the Invention
This invention generally relates to a semiconductor manufacturing process and more particularly to a method for addressing step height issues of a self-alignment process.
2. Description of the Related Art
The semiconductor art has been concerned with reducing the size and power consumption of individual devices and integrated circuits in order to increase the logic power of these circuits per unit area. A particular effort has been made in the area of monolithic random access memories (RAMs) which have very large memory capacities. Many things have been done over the years in an attempt to reduce the size of devices and improve tolerances with which they are fabricated, such as a self-aligned etching process.
A self-alignment process is a simple method for a lithography process. However, self-alignment causes step heights between a poly gate and poly contact. This issue decreases the chemical mechanical polishing (CMP) process window and thus generates bridge issues.